Reading time ( words)
This month’s column will be just a little different. Normally, when I write about controlled impedances, I talk about the two most important points for fabrication relative to controlled impedance. But I rarely talk about controlled impedance at the design level through layout.
When a customer comes to us and asks us to do a preliminary impedance review relative to fabrication, we look for the design to be within 10%. We also look to make sure the traces they call out actually exist on the Gerber files. Many times, due to rounding errors, the drawing and Gerber files do not match.
Recently, a customer asked for a specific line size to be controlled and assumed the fabricator would prefer impedance callouts in whole numbers, so he rounded up – not realizing he had already used that draw size for features you would not control, such as ground fill and thermal ties.
After a phone call, we were able to get to the bottom of it all and discovered that the part had gone through many iterations and the latest line size was not properly represented on the drawing. New drawings were sent and the parts were made with no issues but this required some due diligence on our part. Many fabricators may have used the trace size they specified verbatim and called it good, and with large trace sizes they may get away with it on 50 ohm structures.
What is my point? Don’t be afraid to pick up the phone and ask the customer!
Another very large customer sent two 4-layer boards riddled with differential pairs and no information about any controlled impedances or specific dielectrics. When we asked if these were to be controlled, the customer was most appreciative and realized that some mention of the impedances, threshold and tolerance should have been made initially.
We see so much in the way of assumptions about Dk. Most use a SINGLE number for the entire stackup and call it out as such on a stackup template. Of course, the reality is that each sub-section, depending upon the dielectric distance and make-up, has its own effective Dk and this means modeling mismatches.
Another common issue relative to impedance is unintended co-planar coupling. Frequently, we are asked to do calculations and create a stackup based solely upon a drawing where we cannot see if any co-planar coupling is going on. Even when a customer sends PDFs of the layers, the actual G-sep distance cannot be derived from the PDFs. You will need to see the output Gerber data to accurately model the impedances if co-planar coupling exists.
Even the little things that you may not think impact impedance need to be known at the time of the calculations: things like color and type of mask material. Anything other than the standard green LPI usually is 1.5 to 2X the “normal” mask thickness. With small geometries (.1 mm and below) this extra mask could adversely affect the calculation.
We typically send customers (especially new customers) an impedance checklist asking about co-planar coupling, mask color, copper weights, the line sizes involved, and the threshold and tolerances associated with them.
As fabricators we are also frequently asked to dictate trace widths/spaces/G-seps and dielectrics to meet various customer impedances. This can sometimes be risky without preliminary Gerbers. For example, let’s say the customer asks for specific line sizes to meet various impedances. Obviously from a fabrication standpoint, if we are allowed to dictate lines and dielectrics, we will err towards reasonable sizes and reasonable dielectrics only to find out, for instance, that traces or spaces are .003” or less elsewhere on the design and the outers must be started on lighter copper (such as quarter-ounce copper), which would change all the impedance calculations and perhaps require trace growth not possible with the available space.
A little knowledge and experience on the part of the fabricator can sometimes mean the difference between a “no bid” and accepting a given job. Let me give you another example. Let’s talk about vias – not blind or buried vias, but just plain old vias. Many times at the design and Gerber layout stage, a designer may think a .005” annular ring is adequate, forgetting that a fabricator will drill anywhere between .004” and .005” larger than the finished hole size to be able to plate back down to that size and still meet the IPC min of 8/10 of a mil of copper in the barrels.
If stated as +/-.003” for normal plated through-hole tolerance, sometimes this means a “no bid” at the sales stage, when in reality they are true vias and the drilled size is not really an issue as long as there is continuity. Here, a fabricator can suggest drilling at a smaller size as long as it does not defeat their own drill’s aspect ratio numbers.
Occasionally we see designs that do not fit the standard impedance mold, such as diff pairs with one half of the diff pairs as a serpentine clock-type trace defeating the thought process that says all diff pairs should have the same space between tracks and be of equal length. Or ref planes that only work for half of the diff pairs, or unique ref planes for impedances. We talk a lot about what should be included in the “read me” or drawings, but I can think of no better info to put on a “read me” than the information above. This can mean the difference between getting a call from the fabricator and not getting one.
Now, let’s briefly talk about data types and netlists.
If you have the ability to send either Gerber or ODB++, please send one or the other. If not, it is the fabricator’s responsibility to ensure no differences exist between the two datasets.
Regarding IPC netlists: Lately, we are being asked to run more and more IPC netlists for customers who have never asked for them before. This generally requires a learning curve on their part to indicate “known” or intentional netlist mismatches such as AGND to DGND shorts, or design netlists that take into account post connections from mounting hardware, creating erroneous broken nets when the net-compare is run.
Please let me know if you have any questions or comments. I would LOVE to hear your additional feedback on these topics, and I know they are all subjects people feel strongly about.
Mark Thompson is in engineering support at Prototron Circuits. To contact Mark, click here, or call 425-823-7000.