Since the time of their introduction, area array packaging such as BGAs, area array CSPs, and wafer-level packages have been extolled for their ability to simultaneously improve product performance and assembly yield while reducing overall system cost. Because of these important advantages, the industry was enticed to adapt to area array packaging. The benefits of area array interconnection became abundantly clear when it was realized that the previous generation of packaging solutions based on peripherally leaded packaging concepts would not carry the electronics industry into the future.
As peripherally leaded packages grew in size to support increasing pin counts required by more highly integrated ICs, the packages began sapping device performance while consuming more PCB real estate. Area array packages were promptly recognized as a highly promising solution however there were lots of unanswered questions relative to manufacturing and inspection of these new devices. There was some knowledge but it was limited to OEMs who had embraced area array methods for internal designs.
The industry at large needed to jump on the learning curve and overcome its fear of the unknown. One of the most vexing concerns at the time (and arguably still today) is that terminations beneath the area array package were unseeable. Given the fact that then, as today, solder joints were a major cause of failure, there was much consternation over the quality of the joints. New equipment and methods, such as x-ray inspection, were applied and the industry made rapid progress in developing materials and processes that assuaged those fears and allowed the industry to continue to design and manufacture ever improved products at lower costs.
However, in the industry’s rush to take immediate satisfaction of the benefits of area array packaging, it collectively failed to consider some highly significant overall benefits made possible by area array packaging—the potential to design assemblies with every component having terminations that could land on a standard grid.
To read this entire article, which appeared in the February 2017 issue of The PCB Design Magazine, click here.